A Low Cost and Low Power AES Design

• Main Authors: Huang-Ting Yen, 顏煥庭
• Other Authors: Hui-Tang Lin
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/39632667935383085373

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 94 === With the rapid growth of wireless networks, the data security becomes an important issue. In order to protect data, a general approach is to encrypt the data before transmission. In the past, DES was the most popular encryption mechanism. However, it is found later that DES can not provide adequate security. On November 26, 2001, The U.S.A NIST (National Institute of Standards and Technology) announces a new encryption algorithm – AES to replace DES as the default encryption algorithm because of its strong encryption capability. Now, AES is adopted widely in most communication technologies, especially in the wireless networks which are peculiar vulnerable to eavesdropping. In this thesis, we proposed a low-cost and low-power architecture for AES design for the resource-constrained wireless network. This architecture can reduce the chip area effectively and minimize the power consumption dramatically, while allowing the processing speed to meet the requirements of the wireless network. The netlist is generated by using TSMC .13 um CMOS processes and Synopsys’s Astro. The proposed AES design only demands 12.4K gate counts while achieving 348.58Mbps processing speed. The power consumption is 505.9μW at 10MHz operating frequency.