VLSI Design for Wavelet Based SpeechEnhancement System
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === In this thesis, we focus on the hardware implementation of a wavelet-based speech enhancement system and verify it. It consists of two parts: In the first part we proposed the architecture of analysis and synthesis wavelet packet transform. The folded architec...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19234410910147626771 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === In this thesis, we focus on the hardware implementation of a wavelet-based speech enhancement system and verify it. It consists of two parts: In the first part we proposed the architecture of analysis and synthesis wavelet packet transform. The folded architecture is used to implement the analysis lifting wavelet packet and not need extra memory unit to save the temporary coefficients. The architecture of synthesis wavelet packet transform needs extra memory that has half of frame length. Finally we combined the architecture of analysis and synthesis and compare with other architectures. It proves our architecture has smaller area.
In the second part we proposed two different processing types of speech enhancement system, named real time and non-real time processing respectively. The real time processing has the input from analysis wavelet transform and non-real time processing has the input from the memory. The real time processing has lower latency and the non-real time has smaller area. The proposed architectures are synthesized with TSMC 0.18 um technology. Finally we use ARM development platform to verify our architectures.
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