Wakeup Logic Optimizations and Trade-off in High-performance Superscalar Processors

• Main Authors: Kuo-Su Hsiao, 蕭國樹
• Other Authors: Chung-Ho Chen
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/31350162196367680486

博士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === In a high-performance superscalar processor, the dynamic instruction scheduler often comes with poor scalability and high complexity due to the expensive instruction wakeup operation. This thesis presents three optimizations for wakeup logic to improve the power consumption, wakeup latency, area cost, and scalability. First, a wakeup design that pre-decodes the source tag is proposed. This design removes the reads of the destination tag and eliminates the redundant tag matches by matching the source tag directly with only the selected grant line. Next, the second design exploits the wakeup locality that most of the wakeup distances between two dependent instructions are short. By limiting the wakeup operation within a small wakeup range, the load capacitance and circuit activities can be alleviated. Third, a scheduling technique is proposed to schedule instructions into the segmented issue window based on their wakeup addresses. During wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The experimental results show that the proposed designs save the power consumption, and reduce the wakeup latency compared to the conventional designs. The results also show that the proposed designs have excellent scalability.