Wakeup Logic Optimizations and Trade-off in High-performance Superscalar Processors
博士 === 國立成功大學 === 電機工程學系碩博士班 === 94 === In a high-performance superscalar processor, the dynamic instruction scheduler often comes with poor scalability and high complexity due to the expensive instruction wakeup operation. This thesis presents three optimizations for wakeup logic to improve the pow...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31350162196367680486 |