Design and Implementation of Low Noise Amplifier for 3 to 6 GHz UWB Application
碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 94 === The thesis uses TSMC 0.18 1P6M CMOS process to design and implement the “ four to six GHz LNA ”, “ three to six GHz LNA ”, and “ three to seven GHz LNA. ” The simulate results for Noise Figure（NF）of the three chips are all lower than 5 dB, and S11 or S22 ar...
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| Format: | Others |
| Language: | zh-TW |
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2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10564918503258894547 |
| Summary: | 碩士 === 國立成功大學 === 微電子工程研究所碩博士班 === 94 === The thesis uses TSMC 0.18 1P6M CMOS process to design and implement the “ four to six GHz LNA ”, “ three to six GHz LNA ”, and “ three to seven GHz LNA. ” The simulate results for Noise Figure（NF）of the three chips are all lower than 5 dB, and S11 or S22 are between -5 and -15 dB. On the other hand, I try my best to decrease the device number of three chips. Three chips don’t have traditional RLC feedback or use long LC series and parallel circuits to increase the bandwidth.
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