Design of Clock and Data Recovery Circuits Using aPhase-realignment Oscillation Technique
碩士 === 國立中興大學 === 電機工程學系所 === 94 === The goal of this thesis is to use a standard CMOS process to implement clock and data recovery circuits (CDRs) with an open-loop type,direct data injection lock phase realignment technique. The functions of frequency and phase locking both could be attained witho...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/17805701905393708373 |