| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 94 === The goal of this thesis is to use a standard CMOS process to implement clock and data recovery circuits (CDRs) with an open-loop type,direct data injection lock phase realignment technique. The functions of frequency and phase locking both could be attained without using Hogge’s or Alexander’s phase detector by using this technique.
In the first chip, we present a two-stage ring-type oscillator which could make phase synchronization between oscillator clock and input data in less than five bits time since the first data transition happens. By using techniques of replica and phase locking , a half-rate burst mode clock and data recovery circuit was implemented. From measurement , tuning range of the oscillator is from 1.87GHz to 2.03GHz, the phase noise at 1MHz offset frequency is -112 dBc/Hz when the oscillator is running at 1.87GHz.
In the second chip, a oscillator which could make edge-alignment between oscillator clock’s and input data’s by injection of input random data is presented. Utilizing replica and phase-locked loop technique,direct data injection phase synchronization mechanism would not alter frequency of the oscillator and the optimizing sampling phase could be kept after oscillator is locked to input data . In measurement , input data with length of and bit-rate of 1.55Gb/s is recovered to two 775Mhz parallel data flows with peak-to-peak jitter of 101.5ps and root-mean-square jitter of 14.7ps.
In the third chip,by utilizing direct phase synchronization oscillator and a half rate frequency detector,a reference-less and capacitor-only loop filter clock and data recovery architecture is presented . It not only possessed the characteristic of wide frequency acquistion range in frequency locked loop,but the function to make phase synchronization between input data and oscillator clock .From measurement, we proved the feasibility of this architecture. With input data length of and bit-rate of 2.46Gb/s, the recovered data’s peak-to-peak jitter is 55.56ps and root-mean-square jitter is 9.78ps , phase noise of 1.23GHz recovering clock is -107.5dBc/Hz at 100kHz offset frequency . The power consumption of core circuits is 94mW and area of core circuit is 621um x 418um .
|
|---|
