| Summary: | 博士 === 國立中興大學 === 資訊科學系所 === 94 === Under situations of the same buffer resources deployed in the switch, shared-memory based packet switches compared with other memory managements are known to deliver the best possible performance for bursty data traffic in networks and Internets. Nevertheless, scaling of shared-memory packet switches to a huger size has been limited and they cannot process packets in a high speed network, chiefly because of the physical restrictions imposed by the memory operation rate and the centralized strategy for switching functions in shared-memory switches. In this dissertation, a scalable switch for the high speed network, which is called the parallel packet switch (PPS), is studied to overcome these constraints. The PPS comprises multiple packet switches operating independently and in parallel. The PPS class is characterized by the deployment of parallel center-stage switches with memory buffers running slower than the external line rate. Each lower speed packet switch operates at a fraction of the external line rate R. For example, each packet switch can operate at internal line rate R/K, where K is the number of center-stage switches.
This dissertation develops and investigates a PPS which distributes cells or variable-length packets to low-speed switches and uses outputs with push-in arbitrary-out (PIAO) queues. We present a novel Markov chain model that successfully analyzes and exhibits PPS performance characteristics for throughput, cell delay and cell drop rate. Simulation comparison demonstrates that the developed Markov chain model is accurate for practical network loads and the PPS with PIAO queues provided considerably outperformed previously known classes of shared-memory switch architecture. Additionally, by using this approximate Markov chain, this dissertation analyzes whether a PPS can emulate a first-come first-served (FCFS) output-queued (OQ) packet switch. The major findings obtained using the proposed model are that: (1) the throughput and cell drop rates of a PPS can theoretically emulate those of an FCFS-OQ packet switch when each lower speed packet switch works at a rate of approximately R/K; and (2) the cell delay of a PPS can theoretically emulate that of an FCFS-OQ packet switch when each lower speed packet switch operates at a rate of approximately (R/SF), where SF is the speedup factor.
Finally, in this dissertation, a novel sliding window (SW) packet switching method for PPS, called SW-PPS, is proposed. The conventional PPS dispatch algorithm adopts a round-robin (RR) method. The SW-PPS employs memory space more effectively than the existing PPS using RR algorithm. Under identical Bernoulli and bursty data traffic, the SW-PPS provides significant performance improvement when compared to PPS with RR method. This dissertation presents an analytical model to evaluate the performance of the PPS using RR and SW method. Under various operating conditions, our proposed model and analysis successfully exhibit these performance characteristics.
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