| Summary: | 碩士 === 明新科技大學 === 電子工程研究所 === 94 === This paper presents a study of 5.8 GHz low-noise amplifier (LNA) applied in WLANs with low supply voltage and low power consumption. They are designed by 0.18 μm CMOS process parameters of TSMC, and simulated in Advanced Design System (ADS) of Agilent software.
The dramatic progress of CMOS process technology has gradually evidenced its applications in RF front-end circuit. The process has the advantages of low cost and highly integration. The LNA designed by cascode architecture exhibits the lower power dissipation and higher linearity.
The first LNA circuit is a one-stage amplifier which is designed by source inductor degeneration and cascode structure, it exposes the main features of low power consumption and high linearity. The simulation and analysis results obtained as following: the gain (S21) of 15.2 dB, noise figure (NF) of 2.6 dB, 1-dB compression point (P1dB) of -16.9 dBm, third-order intercept point (IIP3) of -6.4 dBm, and power dissipation 4.96 mW.
The second LNA circuit is two-stage amplifier which is designed by cascoding a simple amplifier to series the first LNA circuit in order to increase the gain. The simulation and analysis results obtained as following: the gain (S21) of 23.8 dB, noise figure (NF) of 2.8 dB, 1-dB compression point (P1dB) of -23.4 dBm, third-order intercept point (IIP3) of -13.2 dBm, and power dissipation 8.6 mW.
We find the emphasized characteristics through analysis for the two groups of circuit are not the same. The first LNA circuit will be designed for low power consumption and high linearity and the second LNA circuit for obtaining high gain mainly. So, we can integrate the structure of receiver according to different characteristics requirement of the LNA.
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