| Summary: | 碩士 === 崑山科技大學 === 電子工程研究所 === 94 === In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture.
The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.3 LSB, DNL is less than 0.25 LSB, settling time is 9 ns, and glitch is 5.8 pV-s. For 1MHz sine wave input and 100 MHz sampling rate, the SFDR is 80 dB, and for 49MHz sine wave input and 100 MHz sampling rate, the SFDR is 67 dB. The power consumption is 127 mW at the maximum conversion rate.
The real world measurement results show that the proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.6 LSB, DNL is less than 0.4 LSB, settling time is 10 ns, and glitch energy is 25 pV-s. For 200 kHz sine wave input and 100 MHz sampling rate, the measured SFDR is 70.3 dB, and for 5 MHz sine wave input and 100 MHz sampling rate, the measured SFDR is 63.51 dB. The measured power consumption is 142 mW at the maximum conversion rate.
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