An Improved and Analysis of High Efficient Positive CMOS Charge Pump

• Main Authors: Cheng-Lun Ting, 丁正倫
• Other Authors: Ying-Wei Jan
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/87004761659520142829

碩士 === 義守大學 === 電子工程學系碩士班 === 94 === A charge-pump is a dc-dc converter that boosts a voltage higher than the system’s power supply voltage. In an SOC system, the higher voltage can be used to speed up the critical path and adjust the threshold voltage of PMOS FET. In addition, flash memory systems or LCD display systems often require a considerable high voltage to work. Charge pumps are widely used in cell phone, PDA and SOC systems. The performance of the charge-pump circuit is evaluated by its pumping voltage gain and energy transfer efficiency. The major factors that will limit the charge-pump gain and efficiency are circuit topologies, MOS transistor threshold voltage drop, and body effect. The dual phase charge-pumps have serious output voltage drop, when clock phases are overlapped. This paper improved a single clock type of charge pump circuit. A circuit to implement charge-pump is analyzed. When the supply voltage is 3.3V and the clock frequency is 10MHz, the proposed charge pump circuit has 0.61% voltage increment and better power efficiency than the conventional one. The analysis of proposed circuit is based on the behavior of TSMC 0.35μm 2P4M CMOS n-well technology. This search is sponsored by NSC 93-2215-E-006-004.