Design and Analysis of A Charge Transfer Current Latched Sense Amplifier Circuit for SRAM
碩士 === 義守大學 === 電子工程學系碩士班 === 94 === Large bit line wire loading is one of the main bottlenecks to the performance of SRAM. We propose a charge-transfer mechanism and a new pre-charge scheme to improve the sensing speed of the traditional current latch sense amplifier. The improvement of sensing spe...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74187884365545419376 |
| Summary: | 碩士 === 義守大學 === 電子工程學系碩士班 === 94 === Large bit line wire loading is one of the main bottlenecks to the performance of SRAM. We propose a charge-transfer mechanism and a new pre-charge scheme to improve the sensing speed of the traditional current latch sense amplifier. The improvement of sensing speed of the proposed design is about 4% comparing to the traditional current latch sense amplifier. In addition, the proposed design has much better tolerance and faster sensing speed on Vt mismatch of NMOS transistors. The presented circuit simulation result is evaluated in the TSMC 0.18μm Mixed Signal/RF Process Model.
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