| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 94 === Most digital system has been an increased growth. To increase the frequency of operation is considered. Timing in high-performance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing timing of the clock period.
The overhead of conventional domino circuit can consume 25% or more of the cycle time in digital systems. The designer can hide much of this overhead through better design techniques. The Skew-tolerant design is avoiding hard edges in which data must setup before a clock edge but will not continue propagating until after the clock edge. Skew-tolerant domino circuits use multiple overlapping clocks to eliminate latches, removing hard edges and hiding the sequencing overhead.
This thesis presents skew-tolerant circuit design, the conventional architecture suffers significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit. This paper presents a design of high-speed Baugh-Wooley multiplier based on skew-tolerant domino.
And we also provide some principles which should be considered in this design. From simulation results, it is demonstrated that the performance is improved.
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