A Schedulable DMA Scheme for Real Time Systems

A Schedulable DMA Scheme for Real Time Systems

碩士 === 輔仁大學 === 電子工程學系 === 94 === It is a key issue for real time multimedia applications to have guaranteed I/O throughput. If the data transfers between the I/O devices and main memories are undertaken by a traditional DMA (Direct Memory Access) mechanism, the real time requirement is hardly satis...

Full description

Bibliographic Details
Main Authors: Chuang Hsiang Huang, 黃莊翔
Other Authors: Kuan Jen Lin
Format: Others
Language:en_US
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/16667304493218026999
id ndltd-TW-094FJU00428003
record_format oai_dc
spelling ndltd-TW-094FJU004280032015-12-23T04:08:00Z http://ndltd.ncl.edu.tw/handle/16667304493218026999 A Schedulable DMA Scheme for Real Time Systems 支援即時系統之可排程DMA機制 Chuang Hsiang Huang 黃莊翔 碩士 輔仁大學 電子工程學系 94 It is a key issue for real time multimedia applications to have guaranteed I/O throughput. If the data transfers between the I/O devices and main memories are undertaken by a traditional DMA (Direct Memory Access) mechanism, the real time requirement is hardly satisfied. This thesis proposes a novel SDMA (Schedulable DMA) mechanism that can guarantee real time I/O throughput as well as interrupt the CPU as few as possible. The I/O task model is formulated and the schedulability for a set of tasks is investigated. The controller handling the SDMA is designed and implemented on the Altera EPXA10 DDR development board, which features an ARM9-based SOPC device. Preliminary experimental result shows the effectiveness of the proposed SDMA controller. Kuan Jen Lin 林寬仁 2005 學位論文 ; thesis 44 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 輔仁大學 === 電子工程學系 === 94 === It is a key issue for real time multimedia applications to have guaranteed I/O throughput. If the data transfers between the I/O devices and main memories are undertaken by a traditional DMA (Direct Memory Access) mechanism, the real time requirement is hardly satisfied. This thesis proposes a novel SDMA (Schedulable DMA) mechanism that can guarantee real time I/O throughput as well as interrupt the CPU as few as possible. The I/O task model is formulated and the schedulability for a set of tasks is investigated. The controller handling the SDMA is designed and implemented on the Altera EPXA10 DDR development board, which features an ARM9-based SOPC device. Preliminary experimental result shows the effectiveness of the proposed SDMA controller.
author2 Kuan Jen Lin
author_facet Kuan Jen Lin
Chuang Hsiang Huang
黃莊翔
author Chuang Hsiang Huang
黃莊翔
spellingShingle Chuang Hsiang Huang
黃莊翔
A Schedulable DMA Scheme for Real Time Systems
author_sort Chuang Hsiang Huang
title A Schedulable DMA Scheme for Real Time Systems
title_short A Schedulable DMA Scheme for Real Time Systems
title_full A Schedulable DMA Scheme for Real Time Systems
title_fullStr A Schedulable DMA Scheme for Real Time Systems
title_full_unstemmed A Schedulable DMA Scheme for Real Time Systems
title_sort schedulable dma scheme for real time systems
publishDate 2005
url http://ndltd.ncl.edu.tw/handle/16667304493218026999
work_keys_str_mv AT chuanghsianghuang aschedulabledmaschemeforrealtimesystems
AT huángzhuāngxiáng aschedulabledmaschemeforrealtimesystems
AT chuanghsianghuang zhīyuánjíshíxìtǒngzhīkěpáichéngdmajīzhì
AT huángzhuāngxiáng zhīyuánjíshíxìtǒngzhīkěpáichéngdmajīzhì
AT chuanghsianghuang schedulabledmaschemeforrealtimesystems
AT huángzhuāngxiáng schedulabledmaschemeforrealtimesystems
_version_ 1718156204582109184

Similar Items