A Schedulable DMA Scheme for Real Time Systems
碩士 === 輔仁大學 === 電子工程學系 === 94 === It is a key issue for real time multimedia applications to have guaranteed I/O throughput. If the data transfers between the I/O devices and main memories are undertaken by a traditional DMA (Direct Memory Access) mechanism, the real time requirement is hardly satis...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/16667304493218026999 |
| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 94 === It is a key issue for real time multimedia applications to have guaranteed I/O throughput. If the data transfers between the I/O devices and main memories are undertaken by a traditional DMA (Direct Memory Access) mechanism, the real time requirement is hardly satisfied. This thesis proposes a novel SDMA (Schedulable DMA) mechanism that can guarantee real time I/O throughput as well as interrupt the CPU as few as possible. The I/O task model is formulated and the schedulability for a set of tasks is investigated. The controller handling the SDMA is designed and implemented on the Altera EPXA10 DDR development board, which features an ARM9-based SOPC device. Preliminary experimental result shows the effectiveness of the proposed SDMA controller.
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