| Summary: | 碩士 === 輔仁大學 === 資訊工程學系 === 96 === Scheduled data flow is a unique architecture. This architecture is based on the concept of dataflow, including the characteristics of decoupling of memory access and the non-blocking multithreading. SDF architecture does not use complicated hardware as von Neumann architecture’s scoreboard and reservation stations for dynamic instruction scheduling. Thus, it is easy to place more units on a single core. In this research we present a notion that increasing the number of units in SDF architecture and comparing with multi-ALU in Simplescalar architecture shows better performance. Simplescalar architecture provides a very complex out-of-order issue superscalar processor. Simplescalar processor’s simulator, which has a two-level memory system, speculative execution and many ALUs that can be supported simultaneously to take advantage of ILP. In our evaluations, with several small benchmarks, demonstrate that the reduction in clock cycles is much better in SDF using multiple units than Simplescalar’s architecture using multiple ALUs. The results presented in this thesis we can see that SDF architecture shows better performance when more units are added. It is useful to add more and more units and can still find the thread level parallelism (TLP) in SDF. Which can be complimented with ILP.
|
|---|
