The Study of Erasing Charge Profiling Distribution in Novel Memory Devices
碩士 === 中原大學 === 電子工程研究所 === 94 === Recently, the discrete charge trapping non-volatile memory (NVM) devices received much attention due to their potential multi-bit storage in a unit cell. In contrast to those floating gate memories, oxide-nitride-oxide (ONO) charge trapping structures are explored...
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| Format: | Others |
| Language: | en_US |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93908362894035476316 |
| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 94 === Recently, the discrete charge trapping non-volatile memory (NVM) devices received much attention due to their potential multi-bit storage in a unit cell. In contrast to those floating gate memories, oxide-nitride-oxide (ONO) charge trapping structures are explored to store charges in NROM and TwinMONOS for high density NVM devices. Newly developed gate-to-drain non-overlapped implementation (NOI) MOSFETs are proposed by using the silicon nitride (SiN) spacers as charge trapping media since the wafer process is fully compatible with the standard CMOS process flow and offer high density that can be cost down efficiently.
This thesis presents the proposed charge pumping (CP) method to study of programming and erasing charge profiling distribution of NOI memory device. To clarify whether the distribution uniformity if interface state has severe or limited impact on the accuracy of lateral charge profiling in the NOI nMOSFETs. First of all, we introduce the NOI memory device operations and principles. To well understand not only how to utilize the Channel hot electron injection to achieve the Programming but also to erase the data by performing the band-to-band tunneling method. Furthermore, the NOI’s charge profiling investigation is extremely valuable to fully understand its carrier injection mechanism, future scalability and reliability degradation caused by channel hot electrons.
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