| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 94 === Embedded Systems have the principles of high-performance, low-power consumption and low hardware cost, apply for mobiles or information appliances. From 1983, ARM Ltd. published ARM Instruction Set Architecture Version 1 (ARM ISA v1). It supports flexible code design, expandable instruction format, and difference extended instructions with the rapid growth of technology. It had be welcome from embedded system developers and system-on-chip designers. After many years later, for 32-bit RISC CPU (SuperH, M32R, MIPS16) on the market, the ARM family accounts for approximately 75% of all system core. From portable devices (PDAs, mobile phones, handheld gaming units) to computer devices, it became very important role on the market share. Today, ARM ISA v5 has extends instructions, that system develops could select Thumb, Javelle, DSP, VFP, TrustZone, etc. if they want. And if the processor has not enough functions to use, they could choose coprocessor to solve it. Furthermore, it could control cache and memory management unit.
In this paper, we stand on “ARM Architecture Reference Manual, 2nd” which published by ARM Ltd. We design a 32-bit RISC 5-stage pipelined microprocessor. Besides, we analyze the ARM ISA v5 instruction set and 5-stage pipelined architecture.
Finally, we have some proposals for ARM future work in this paper. Under a pipelined architecture, every stage must have the same gate-delay time. But if increasing operations, it usually loaded on Execute stage. So, it need pipelined which 6-stage or higher, and it need parallel data-flows which “Data-Processing Operands” and “Load and Store” instructions to average delay time on every stage.
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