Hole confinement in double-channel SiGe PMOSFET
碩士 === 正修科技大學 === 電子工程研究所 === 94 === A working p-type SiGe metal-oxide-semiconductor field effect transistor (pMOSFETs), utilizing a double quantum wells as the buried conducting channel, has been successfully fabricated. The upper quantum well with 15%-Ge acts as a induced-carrier buffer to slow ho...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/71039114370025604107 |
| Summary: | 碩士 === 正修科技大學 === 電子工程研究所 === 94 === A working p-type SiGe metal-oxide-semiconductor field effect transistor (pMOSFETs), utilizing a double quantum wells as the buried conducting channel, has been successfully fabricated. The upper quantum well with 15%-Ge acts as a induced-carrier buffer to slow holes into the Si surface channel and increases the number of high-mobility holes in the 30%-Ge well at the bottom under high gate voltage by improving carrier confinement. Experimental results show that the devices with thinner Si-spacer layer between the two SiGe quantum wells exhibit excellent property of not only a higher effective hole mobility and wider gate voltage swings due to the better carrier confinement, which shows great potential for RF applications that require high speed, and high linearity.
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