Design of Power-saving Analogy-to-Digital Converter Applying to IEEE 802.11a WLAN
碩士 === 中華大學 === 電機工程學系碩士班 === 94 === This paper is on designing 10-bit, 40MS/s CMOS pipelined power-saving analog-to-digital converter applying to the system of IEEE 802.11a. Firstly, we know that most power consumption of ADC takes place at OTA itself, so decreasing the current consumption of OTA i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28492861782608408939 |
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