| Summary: | 碩士 === 中華大學 === 電機工程學系碩士班 === 94 === This paper is on designing 10-bit, 40MS/s CMOS pipelined power-saving analog-to-digital converter applying to the system of IEEE 802.11a. Firstly, we know that most power consumption of ADC takes place at OTA itself, so decreasing the current consumption of OTA is the point of this design. Next, we are going to discuss the construction and the components of this pipelined ADC. Owing to using Continuous Common Mode Feedback, Bandgap Reference Circuit, and Digital-Error-Correction Technique, we design this ADC by using less-sensitive fully-differential dynamic comparator, the great merit of which is non-static power construction and better noise-immunity. OTA itself consumes 4.13046282mW which achieves simulating in the process of TSMC 0.18 μm.
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