A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems

碩士 === 中華大學 === 電機工程學系碩士班 === 94 === This work describes an analog-to-digital converter which has 10 bit resolutions and 40MHz sampling rate. This analog-to-digital (ADC) converter is used nine-stage pipelined and fully differential structure. Because of the digital error correction is adopted in th...

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Bibliographic Details
Main Authors:	Wei-Zhi Liao, 廖偉智
Other Authors:	Ching-Cheng Tien
Format:	Others
Language:	zh-TW
Published:	2006
Online Access:	http://ndltd.ncl.edu.tw/handle/74906275263764252858

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spelling	ndltd-TW-094CHPI04420292016-06-01T04:15:07Z http://ndltd.ncl.edu.tw/handle/74906275263764252858 A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems 應用於WiMAX之類比數位轉換器設計 Wei-Zhi Liao 廖偉智碩士中華大學電機工程學系碩士班 94 This work describes an analog-to-digital converter which has 10 bit resolutions and 40MHz sampling rate. This analog-to-digital (ADC) converter is used nine-stage pipelined and fully differential structure. Because of the digital error correction is adopted in this ADC, the first eight stages output 1.5 bit at every pipelined stage and the nine stage output complete 2bit. This ADC consists of the sample-and-hold(S/H) circuit, eight MDAC circuits, register circuit, digital error correction circuit, clock generator circuit and two sub-ADC circuits. The sub-ADC circuit consists of comparators and coders. The working range which this pipelined ADC can operate is -1V to 1V. This ADC is simulated by using TSMC 1P6M 0.18um process. Ching-Cheng Tien 田慶誠 2006 學位論文 ; thesis 58 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中華大學 === 電機工程學系碩士班 === 94 === This work describes an analog-to-digital converter which has 10 bit resolutions and 40MHz sampling rate. This analog-to-digital (ADC) converter is used nine-stage pipelined and fully differential structure. Because of the digital error correction is adopted in this ADC, the first eight stages output 1.5 bit at every pipelined stage and the nine stage output complete 2bit. This ADC consists of the sample-and-hold(S/H) circuit, eight MDAC circuits, register circuit, digital error correction circuit, clock generator circuit and two sub-ADC circuits. The sub-ADC circuit consists of comparators and coders. The working range which this pipelined ADC can operate is -1V to 1V. This ADC is simulated by using TSMC 1P6M 0.18um process.
author2	Ching-Cheng Tien
author_facet	Ching-Cheng Tien Wei-Zhi Liao 廖偉智
author	Wei-Zhi Liao 廖偉智
spellingShingle	Wei-Zhi Liao 廖偉智 A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems
author_sort	Wei-Zhi Liao
title	A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems
title_short	A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems
title_full	A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems
title_fullStr	A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems
title_full_unstemmed	A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems
title_sort	10 bit 40ms/s pipelined analog-to-digital converter for wimax systems
publishDate	2006
url	http://ndltd.ncl.edu.tw/handle/74906275263764252858
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A 10 Bit 40MS/s Pipelined Analog-to-Digital Converter for WiMax Systems

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