| Summary: | 碩士 === 中華大學 === 電機工程學系碩士班 === 94 === Abstract
With the rapid growth of modern communication applications and computer technologies, image compression is increasingly in demand. From the compression point of view, transform coding is superior to linear predication coding. Walsh-Hadamard transform is the simplest one, in which the computations involved in the kernel matrix are only additions and subtractions. As cosine transform approximates to the optimal Karhunen-Loeve transform, which is however much more complicated in practice, discrete cosine transform (DCT) has been widely used in the image compression task. Moreover, DCT is adopted by the JPEG standard.
Two-dimensional discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) have been widely used in many image processing systems. In this paper, efficient architecture with parallel and pipelined structures are proposed to implement 8x8 DCT and IDCT processors. In which, dual-bank of SRAM (128 words) and single bank of SRAM (64 words),the coefficient ROM (6 words) is utilized for saving the memory space. The kernel arithmetic unit, i.e. multiplier, which is demanding in the implementation of DCT and IDCT processors, has been replaced by simple adders and shifters based on the double rotation CORDIC algorithm. The proposed architectures for 2-D DCT and IDCT processor not only simplify hardware but also reduce the power consumption with high performances.
The proposed parallel-pipelined architecture for 2-D DCT and IDCT processors have been written in Verilog® and synthesized by TSMC 0.18μm 1P6M CMOS cell libraries. Finally, the layout of the design is generated automatically by the Astro Layout Tools in a 0.18μm 1P6M CMOS technology. The core sizes and power consumptions can be obtained from the reports of Synopsys® design analyzer and PrimPower®, respectively.
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