VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters

• Main Authors: Cheui-Lu Chiu, 邱垂祿
• Other Authors: Tze-Yun Sung
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/87912371214070891187

碩士 === 中華大學 === 電機工程學系碩士班 === 94 === In the field of digital image processing, the JPEG-2000 standard uses the discrete wavelet transform for image compression; hence, the two-dimensional (2-D) forward discrete wavelet transform (FDWT)/ inverse DWT (IDWT) has recently been used as a powerful tool for image coding/decoding systems. 2-D FDWT/IDWT demands massive computations, hence, it requires a parallel and pipelined architecture to implement high-efficiency application-specific integrated circuits (ASIC) or field programmable gate array (FPGA). At the heart of the analysis stage of the system is the FDWT. In the synthesis stage, the IDWT recovers the original image from the coefficients of FDWT. This paper proposes two architectures with computing time for 2-D FDWT and IDWT. The first high-efficiency architecture comprises a transform module, an address generator, and a RAM module. The transform module has uniform and regular structure, simple control flow. The second architecture features parallel and pipelined computation and high throughput, both of the proposed architectures are 100% hardware-utilization and suitable for 2-D digital image processing, such as JPEG-2000. The proposed VLSI architectures are realized with Verilog HDL, synthesized by the Synopsys Design Compiler. Finally, the layouts for those designs are generated with the Synopsys Astro Tools in a 0.18 1P6M CMOS technology.