| Summary: | 碩士 === 中華大學 === 電機工程學系(所) === 94 === This work describes an analog-to-digital converter which has 10 bit resolutions and 40MHz sampling rate. This analog-to-digital (ADC) converter is used nine-stage pipelined and fully differential structure. Because of the digital error correction is adopted in this ADC, the first eight stages output 1.5 bit at every pipelined stage and the nine stage outputs complete 2bit. This ADC consists of the sample-and-hold(S/H) circuit, eight MDAC circuits, register circuit, digital error correction circuit, clock generator circuit and two sub-ADC circuits. The sub-ADC circuit consists of comparators and coders. The working range which this pipelined ADC can operate is -1V to 1V. This ADC is simulated by using TSMC 1P6M 0.18um process.
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