The Design Techniques for Detecting Power and Ground Noise in Integrated Circuits

• Main Authors: Zhi-Hau Hor, 何志浩
• Other Authors: 周煌程
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/22518615495833491301

碩士 === 長庚大學 === 電子工程研究所 === 94 === With the advancement of processing technology of integrated circuits(ICs), the channel length of transistor becomes shorter and the circuit can work faster. The threshold voltage and power supply both become lower to reduce the power consumption. However, the density per unit area becomes higher. In high density ICs, the spacing is shortened between circuits and therefore the interaction effect increases. The power supply is lowered, but the noise becomes relatively larger. The noise immunity is greatly reduced. Therefore, the research of noise effects becomes more and more important. Two new methods have been proposed in this thesis to detect the power supply and ground noise: 1. A modified peak detector sample and hold circuit is presented first. The proposed circuit can detect the maximum noise and holds its value. The circuit is verified able to detect the power supply and ground noise of 1GHz of the magnitude from 10% to 45% VDD. As compared to the prior art, both the detection range and speed are improved significantly. 2. Another proposed circuit can detect the power and ground noise of the frequency up to 4GHz. With small power and area for this circuit, the proposed circuit is easily to be arranged in a chip to detect the noise magnitude of different blocks.