| Summary: | 碩士 === 長庚大學 === 資訊工程研究所 === 95 === The multi-banked register file (MBRF) is one of the effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage scaling (DVS) approach for MBRF to satisfy the energy constraints. However, we found that distributed bank-access behavior prevents voltage scaling from identifying when a bank is active or not. To resolve this problem, in this paper, we analyze the access behavior of short-lived values, and change their storage in banks. The goal is to increase the opportunities of power saving for register banks storing non-short-live values. We then turn these register banks into the lower mode by our proposed DVS circuit. For a four-banked register file architecture, simulation results show that, on average, our approach reduces about 84% energy consumption while performance loss can be limited by less than 10%, compared with a register file without DVS.
|
|---|
