PVT-Tolerant CMOS Level Converters
碩士 === 國立中正大學 === 電機工程所 === 94 === In this thesis we propose “Heuristic Transistor Sizing Guidelines“ to shorten the design time and encrease the design confidence of CMOS level converters(LC). Based on the developed design guidelines, we can systematically observe the performance of LCs under diffe...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52767413142949322217 |