| Summary: | 碩士 === 國立中正大學 === 電機工程所 === 94 === In this thesis we propose “Heuristic Transistor Sizing Guidelines“ to shorten the design time and encrease the design confidence of CMOS level converters(LC). Based on the developed design guidelines, we can systematically observe the performance of LCs under different process corners and different supply voltage offset for a wide temperature range in different Sub-micron and Nano CMOS Processes. Our analysis shows the LC is much more sensitive to PVT variations than commonly used logic gates such as the inverters, NAND gates, and NOR gates. This effect will severely affect the effectiveness of a dual-VDD CMOS design. In order to reduce the influence of PVT variations, we propose two PVT-Tolerant CMOS level converters for Full-custom design and Cell-based design, respectively.
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