| Summary: | 博士 === 國立中正大學 === 電機工程所 === 94 === Traditionally, in order to simplify the highly complex design flow of VLSI chip, EDA tools often separated the flow of chip design into distinctive stages, such as high level synthesis, logic synthesis, and physical design, etc. However, those mutually un-related phases of design are increasingly incapable to handle the much complicated problems encountered in the deep submicron SOC era, in which the dominant factor affecting performance of the chip is mainly on the wire delays instead of the gate delays. As a result, a new design paradigm that simultaneously considers the properties of different design stages is popular in recent years. This dissertation investigates the integration of logic synthesis and physical design for performance improvement of combinational circuits. The pivot concept used in our approach for the logic-physical co-synthesis is a technique of circuit partitioning called maximal super-gates (MSGs).
In the logic aspect of co-synthesis, first, with the help of MSG partitioning, the circuit can be transformed to a globally trees locally non-trees structure, which contrasts with the locally trees globally non-trees structure in traditional tree-based technology mapping. This structure enables us to globally perform dynamic programming technology mapping on the circuit. Besides, by way of delay analysis, the nodes in circuit can be divided into two groups, the ones belonging to the timing critical MSGs and the others belonging to the timing non-critical MSGs. This separation of nodes allows the individual MSG to be manipulated in different way. In our approach, the nodes belonging to timing critical MSGs are matched in a way allowing gate duplication to reduce the circuit delay, while those belonging to the timing non-critical MSGs are matched without duplication to minimize the area penalty. In addition, to enrich the design space for the technology mapping, graph matching instead of tree matching can be applied in each MSG, while the partitions per se can largely alleviate the computational complexity problem imposed by the graph-matching algorithm. Experimental results on the ISCAS’85 benchmarks show that our approach delivers an average of 20.6% reduction on delay with only 9.5% increase on area.
In the physical design aspect of co-synthesis, two salient characteristics of MSG partitioning are especially valuable. First, the MSG forms a natural cluster of circuit, i.e., the strongly connected wires are confined in the MSGs. Second, the inputs to MSG are mutually logic independent. The former property relieves the burden of placement tools whose goal is set to place the close connected cells together and the latter property provides more degrees of freedom to place the input blocks of MSGs. In this dissertation, we propose a dynamic programming mechanism for placement algorithm, which solves the standard cell placement for the combinational circuit of random logic. During the post-order traversal of MSG trees, the MSG blocks are treated as soft macro-cells and a design space exploration algorithm is invoked to generate a variety of design alternatives for the MSGs. The final placement of the circuit is determined in the pre-order traversal process, which picks the best implementation of placements and runs a row-merging algorithm to merge the row placement with that of its parent MSG block. Although we have not yet finished the experiments, we believe that the proposed dynamic programming approach is very promising for the performance driven standard cell placement.
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