Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 94 === Today, the designs of system-on-a-chip (SoC) consist of embedded software running on multiple processor cores, connected to memory and other peripherals. The increasing complexity of systems, it implies more software need to be implemented and being aware of time-to-market pressure. The software engineers needed to search for several new approaches that can cope with the gap between the complexity and productivity. To overcome this problem, the obvious solution is raising the levels of abstraction. Indeed, the primary goal of transaction level model (TLM) is to dramatically increase the simulation speed. It reduces not only the data transfer payload, but also the detailed information that must handle. Although it can accelerate the simulation speed, it still needs to pay something, especially the timing accuracy. For some specific purposes of the application, it becomes an important issue to decide which abstraction level is desired to execute on. But currently, the abstraction level has been decided in static. Sometimes, the software developers only need to observe a few code segments during execution. Therefore, the dynamically switching mechanism is proposed in this work. The major work is switching the hardware abstraction models in run-time, especially the Instruction Set Simulator (ISS), to gain more significant information for debugging and omit the unnecessary notion of time and detailed information for high simulation speed and early embedded software development. In the approach, a controller, a transactor and a monitor are needed. The major work of controller is sending the control signal to the corresponding component according to the switching mechanism in run-time. The transactor needs to connect with the different abstraction models that ensure the communication working. The monitor is a Read-Only component that observe the information of ISS or other components. To prove the feasibility of the proposed approach, an implementation example of simple SoC consisted of single cycle processor, memory and other peripherals is presented in this article.
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