A Design of Simultaneous Multithreading RISC Processor with Non-blocking Load/Store

• Main Authors: Hao-sheng Chen, 陳顥升
• Other Authors: Tien-Fu Chen
• Format: Others
• Language: en_US
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/04996868052452598620

碩士 === 國立中正大學 === 資訊工程所 === 94 === This paper proposes a simultaneous multithreading RISC processor with non-blocking load/store. Many applications exhibit multi-tasking characteristics, such as parallel data operations in video and audio codec. But traditional RISC processor can not take advantage of this inherent parallelism. Instead, multithreading technique enables more than one instruction string to be active in the CPU. Its ability to share hardware resource and hide memory latency would improve performance and efficiency. While multithreading processor is good at multi-processing, it has the limit on issuebandwidth and throughput. In this thesis, we design a 4-way, 2-issue SMT RISC processor to improve that with low design complexity and low area increment incurred. Besides, we also provide non-blocking load/store to hide memory latency. Finally, the clock rate of SMT RISC processor can reach of 210MHz.