| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 93 === In this thesis, we propose three kinds of array processors that detect the vertical symmetry axis for patterns in the image. Based on the detected symmetry axis, the symmetric pattern can be further extracted.
In the first design, we use two n-bit shift-registers to process n bits of input image data in one row, and connect the image data in the near-coincident positions of the two shift-registers to the two-input AND gates. By shifting the data of two shifter registers in two opposite directions, all the midpoints of edge-point pairs in the same row can be generated. To have a faster processor response, the second design links all the possible pairings of the row image data by the 2-input AND gates. It makes use of the hardwired-OR circuits to combine the AND-gate outputs for the same midpoint position through the ingenious IC layout placement. Thus, without costing too much chip area, we can acquire all the midpoints of the given row generated within one clock period.
In the third design, we input the edge-point image data column by column (that is, pixel by pixel sequentially with respect to each row). By connecting the input shift-register of each row to another shift-register that shifts in the reverse direction, the encountering of all the edge-point pairs in the same row can be achieved. Though the hardwired-OR circuit combining the pairing AND gates, the alternating shifts of the two shift-registers sequentially generate the midpoints of all edge-pairs in each row.
With the collection of midpoint information, our parallel circuits accumulate the midpoint count at each column position of the image. If the count value of a column position is greater than the given threshold, then this coordinate is taken as where the pattern’s vertical symmetry axis locates. Based on the location of detected symmetry axis, our system retrieves the image data of each corresponding two columns on two sides of the axis. And by taking some logical operations, the symmetric patterns can be extracted.
In order to correctly evaluate the ease of layout placement, chip area, and the actual performance for the above array processors, we realize the major parts of our designs as IC chips. We adopt the TSMC 0.35μ Mixed Signal (2P4M) CMOS technology and the full custom design to implement the second and third array processor design. The IC layout and Hspice simulation of the second design have been complete and successful, while the fabricated chip of the third array processor design has been physically tested and verified to be successful.
Keywords： Array Processor, Symmetry Axis, Symmetric Patterns , Parallel Processing
|
|---|
