| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === Traditional low speed I/O is progressively replaced by Low Voltage Differential Signaling (LVDS) Interface. In recent years, the third generation I/O PCI Express will become major standard I/O architecture and will become main motherboard architecture in the future. So the interface face with serial transfer is important. Further the complexity of SoC is more and more. There needs advance technology on Link architecture system, circuit design method and design rule flow for SoC. Becoming serial transmission is target. In this thesis, it develops the link architecture for complete packet switching protocols on NoC. Using method of segment function on layer in internet system application to NoC(Network on Chip). In protocol design it includes Transaction layer, Data link layer and Physical layer. It supports the function of flow control, error retry, etc. The capability of transaction layer is accept read or write request of IP. And build a request packet delivers to the Data link layer. The duty of Data link layer is ensuring that packet transfer is correct and reliable. Using data link layer packet to product response of ACK or NACK and support information of flow control. The work of physical layer is supported transmission of serial at point to point. Bring up the extendable hardware design to contain variety system platform. We also use a software tool to design NoC interface which allow to user design. Purpose is to attain high speed transmission of SoC in feature. The layout of the SPNI instance described above, which has an area of 0.82 mm2 in a 0.18-μm technology.
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