The Research of Low-Voltage Double-Sampled Pipelined Analog-to-Digital Converter

• Main Authors: Shen-Hau Yu, 余紳豪
• Other Authors: none
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/18854697367701859793

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 93 === In recent years, high-resolution analog-to-digital converters (ADCs) are required in the front-end receive path of many modern communication systems. Because of the systems portability, power dissipation is becoming an increasingly important design issue in analog-to-digital converters. The aim of this thesis is to investigate the design techniques of pipelined ADCs for low voltage, low power and high sampling rate applications. The targeted architecture is a 10-Bit, 40Msamples/s, 9-stage pipelined ADC with the double-sampling employed. The pipelined ADC consists of the clock generator, sample-and-hold circuit, sub-ADCs, sub-DACs, subtractors, gain stages, decoders, registers, digital error correction circuits and multiplexers. In this research, the double-sampling ADC has been designed with standard TSMC 0.35um CMOS 2P4M process. Simulation results show that under the 1.5V power supply and the input range of ±0.5V, the designed pipelined ADC can operate at 40MHz with 59dB signal-to-(noise+distortion) ratio conforming to the 10-Bit accuracy, and the estimated power dissipation is about 32mW. Total layout area is about 3500×1750um2.