ANALYSIS AND DESIGN OF A CMOS FREQUENCY SYNTHESIZER FOR 802.11a
碩士 === 大同大學 === 電機工程學系(所) === 93 === This thesis designs a frequency synthesizer for IEEE 802.11a standard. The frequency synthesizer consists of a phase detector, a charge pump, a loop filter, a LC-tank VCO which has quadrature phase output, and a pulse-swallow frequency divider. The LC-tank voltag...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33691824154956404731 |
| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 93 === This thesis designs a frequency synthesizer for IEEE 802.11a standard. The frequency synthesizer consists of a phase detector, a charge pump, a loop filter, a LC-tank VCO which has quadrature phase output, and a pulse-swallow frequency divider. The LC-tank voltage-controlled oscillator adopts double cross-coupled pairs in order to get larger output voltage swing and lower phase noise. The quadrature phase output of VCO constructs from two individual VCOs combined by two series transistor pairs. The dual-modulus prescaler which is implemented by TSPC logic can reduce power consumption, achieve higher operation frequency and use less chip area. The program counter with swallow mechanism uses the same register in order to reduce chip area and power consumption. It can differentiate the counted value by combinational logic and the synthesizer still has accurate output frequency. The frequency synthesizer is simulated by TSMC 0.18- single poly, six-metal CMOS process. The ADS simulation results justify the feasibility of the proposed frequency synthesizer.
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