| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 93 === Bandpass ΔΣ converters have been used widely in RF communication systems and instrumentation filed due to the ability to obtain high resolution in the band of interest compared to the traditional Nyquist-rate converters. Delta Sigma modulation with a single-bit quantizer is inherently linear, but unfortunately also causes the quantization noise power to be quite large. It can be reduced by using a multi-bit quantizer if the nonlinearity error introducted by component mismatches of DAC can be solved.
Feedforward delta-sigma topologies have important system- and circuit- level advantages over traditional topologies. It is easy to implement multi-bits with less complexity and physical area for this topology. Additionally, double-sampled switched-capacitor (SC) technique provides a good method of increasing the sampling frequency without many efforts and relaxes the requirement of the Opamp.
In this thesis, a double-sampled 3-bit fourth-order bandpass delta-sigma modulator based on the feedforward topology is proposed. The design flow corresponding to the CAD tools is as followings. Using MATLAB, the optimal parameters are obtained by the system-level simulation. Then, the transistor level simulation with foundry device model is implemented by HSPICE. Finally, the layout of the whole circuit is accomplished with Virtuoso of CADENCE. The clock frequency is 50MHz (effective frequency would be 100MHz). The input signal bandwidth is 1.25MHz centered at 25MHz. The simulation results using HSPICE present a SNR of 60.58dB with -9dBFS input and power consumption of 155.2mW. The modulator is simulated by using the SPICE models of TSMC 0.35μm CMOS 2P4M process.
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