| Summary: | 碩士 === 大同大學 === 通訊工程研究所 === 93 === A great interest has been gained in recent years by a new error-correcting code technique, known as “turbo coding,” which has been proven to offer performance closer to the Shannon’s limit than traditional concatenated codes. Turbo coding offers excellent capabilities of error correction and thus has been getting popular in the wireless applications. However, the implementation of turbo coding requires high computing power and large memory size. In this thesis, we present the design and implementation of 3GPP turbo code. We use the sliding window technique and memory architecture to reduce the complexity and implement turbo decoder on Xilinx Virtex II Pro xc2VP50. The clock frequency of our decoder system can achieve 50MHz. When SNR is 1.5dB, our decoder system BER is close to 10-5.
|
|---|
