A Novel Reseeding Mechanism for Pseudo-Random Testing of VLSI Circuits
碩士 === 淡江大學 === 電機工程學系碩士班 === 93 === During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove usele...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10234374848688795657 |