A Novel Reseeding Mechanism for Pseudo-Random Testing of VLSI Circuits

• Main Authors: Ying-Fu Ho, 何應甫
• Other Authors: Jiann-Chyi Rau
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/10234374848688795657

碩士 === 淡江大學 === 電機工程學系碩士班 === 93 === During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change from them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random and use an additional bit counter to improve test length and achieve high fault coverage. The fact that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we pick out number of different less bit, leading to very short test length. And We can use an additional bit counter to control the scan enable signal for capturing (when the useful pattern is loaded into the scan chains). The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% faults coverage can be achieved. Modern design and package technologies make external testing increasingly difficult and the built-in self-test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. The main components of a BIST scheme are the test pattern generator (TPG), the response compactor, and the signature analyzer. The test generator applies a sequence of patterns to the circuit under test (CUT), the responses are compacted into a signature by the response compactor, and the signature is compared to a fault-free reference value. In this paper, we used an additional bit counter to control the scan enable signal. When the counter achieve to zero, it means that the useful pattern is loaded to the scan chain, so we can disable the scan enable signal for capturing. We pay the price in hardware overhead in order to decrease test length.