Design and Implementation of Dual-Feedback Phase-Locked Loop
碩士 === 淡江大學 === 電機工程學系碩士班 === 93 === Phase-locked-loops (PLLs) are widely used in wireless data telecommunications, such as wireless local area networks (WLANs), mobile and satellite communications. In these applications, the PLLs are usually used as a clock synthesis block to generate a high-speed...
Main Authors: | Yi-Shun Shih, 史義順 |
---|---|
Other Authors: | 郭建宏 |
Format: | Others |
Language: | en_US |
Published: |
2005
|
Online Access: | http://ndltd.ncl.edu.tw/handle/68329258151298912821 |
Similar Items
-
Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop
by: Chung-Ting Lu, et al.
Published: (2007) -
Design and Implementation of 1-Volt GHz and Fast-Locking Phase-Locked Loop
by: Shu-Chang Kuo, et al.
Published: (2004) -
DESIGN AND IMPLEMENTATION OF A PHASE-LOCKED LOOP CIRCUIT
by: Han-Jie Ma, et al.
Published: (2013) -
Design And Implementation Of High-Bandwidth Phase-Locked Loop
by: Jian-Ji Zhang, et al.
Published: (2012) -
Design and Implementation of Phase-Locked Loop With Cyclic Clock Generator to Enhance Loop-Bandwidth
by: Chuang,Yi Hsien, et al.
Published: (2012)