The IP Generator of High-Speed Fuzzy Inference Processor

• Main Authors: Ming-Wei Lan, 藍明偉
• Other Authors: Shung-Chih Chen
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/37101911801833548424

碩士 === 南台科技大學 === 電子工程系 === 93 === In the past few years, there has been a lot of aggressive developments in fuzzy field, such as GPS data processing, air-conditional control, image processing, and so on. Even though, many fuzzy systems still exist slow inference speed or less flexibility problems which limit the applications of the fuzzy systems. In the fuzzy systems, the fuzzy rules are characterized by membership functions. Therefore, when designing a fuzzy system, we need to have an effective methodology to synthesis the membership functions. In the thesis, we made some improvements over the past fuzzy systems in three parts. For the membership function generation, a simple hardware has been designed to quickly generate either triangle-shaped or trapezoid-shaped membership functions; In the fuzzy inference part, only the inferred rules, instead of all rules, are activated and used for inference to shorten the inference time; In the defuzzification part, the calculation of center of gravity (COG) has been simplified to speedup the defuzzifier. In comparison with traditional fuzzy systems, our system only requires 4 system clocks to complete the defuzzification instead of 128 clocks that a traditional fuzzy system needs. To make the system more flexible, a software interface has been developed to generate variable soft FLC IPs (Fuzzy Logic Control Intellectual Properties). Users can set the numbers of membership functions of input variables, output variables, and fuzzy inference rules, and set the slopes of the membership functions. Once these parameters are set by users, the corresponding Verilog codes are generated and can be downloaded to FPGA chips, in our system which is the Altera FLEX 10k50EQC240-3 chip. Through the FLC IP generator interface, users can design the suitable chip what they need. An FLC controller with 2 inputs and 1 output, each has 5 membership functions, has been synthesized by the TSMC 0.35 um standard cell. It can work at the speed of 40M Hz clock rate and 10M FLIPS (Fuzzy Logic Inferences Per Second). When comparing with other FLCs, ours can get better performance and higher flexibility.