A Low-Cost VLC Algorithm and Its VLSI Architecture for MPEG-4

• Main Authors: Yi-Ming Lin, 林宜民
• Other Authors: Shung-Chih Chen
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/46803603763343972468

碩士 === 南台科技大學 === 電子工程系 === 93 === Variable-length coding (VLC) is a very popular lossless compression method. In this paper, we present a low-cost VLC algorithm and its VLSI architecture for MPEG-4. For encoding input symbols, two smaller tables, symbol-location table and section-based codeword table, are adopted in place of a large codeword table as most traditional methods did. The symbol-location table contains the locations of all possible input symbols. Then those symbols’ codewords are divided into different classes and sections, and store the most representative codeword for each section in section-based codeword table to reduce largely the required storage space. Compared with previous methods, our VLC method can reduce about 58.5%~74% memory size, and thus needs lower hardware cost. For real-time MPEG-4 applications, the VLSI architecture of our VLC method is designed and implemented by Artisan UMC 0.18 cell library. In our synthesis results, the VLC encoder and decoder contain 7885 and 9354 gate counts respectively, and both work with a clock rate of 100 MHz.