| Summary: | 博士 === 國立臺灣大學 === 電機工程學研究所 === 93 === As technology advances into nanometer territory, the paradigm shift of the routing problem is indispensable to cope with three major challenges: design complexity, signal-integrity problem, and manufacturability problem.
As Moore''s Law continues unencumbered into the nanometer era, chips are reaching 100 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing- aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly support the ever increasing design complexity, and be capable of adapting to the requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In this Dissertation, we propose a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization.
To handle the ever increasing design complexity of gigascale integration, the mSIGMA use a multilevel framework that has attracted much attention in the literature recently. The traditional multilevel framework employs a two-stage technique: coarsening followed by uncoarsening. The coarsening stage iteratively groups a set of circuit components (e.g., circuit nodes, cells, modules, routing tiles, etc.) based on a predefined cost metric until the number of components being considered is smaller than a threshold. Then, the uncoarsening stage iteratively ungroups a set of previously clustered circuit components and refines the solution by using optimization techniques.
Different with the previous multilevel routing framework, we introduce an intermediate track assignment phase between coarsening and uncoarsening stages, to
improve run-time and achieve optimization.
To handle the signal-integrity problem, especially the crosstalk problem, we propose a fast layer/track assignment heuristic for crosstalk optimization. We first build the horizontal constraint graph (HCG) for all segments in the panel. For the crosstalk-driven layer assignment problem, we resort to a simple yet efficient heuristic by constructing a maximum spanning tree from the given HCG. Since a tree can be k colored in linear time if we have k layers, we shall first partition the vertices incident on edges with larger costs (coupling lengths) and allocates the corresponding segments to different layers. Then, our track assignment algorithm starts by finding the maximal sets of conflicting segments, and assigns these conflicting segments by the bipartite assignment graph till they are assigned in the panel.
To handle the manufacturability problem, such as process antenna effect and the X-architecture, we also propose a desirable track assignment in our multilevel routing framework for manufacturability optimization. To solve the antenna effect, we propose a built-in jumper insertion approach for antenna effect avoidance. To take the advantage of the X-architecture, we also adopt our new multilevel routing framework for the X-based architecture, and the experimental results show the promise of wirelength and delay reduction.
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