| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === This thesis proposes a segment weighted random (SWR) BIST technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transitions are minimized. In addition, scan cells in segments of the same weight are reordered to further reduce the scan-out transitions. The penalty of this technique is area and routing overhead for scan chain reordering.
This thesis also presents a low power DSSS digital receiver design. The modulation scheme is QPSK. The receiver obtains partial symbols form the analog correlator. The receiver consists of two major blocks: CFO estimator and carrier recovery loop. The feature of this receiver is that it eliminates the carrier frequency offset (CFO) and the timing offset (TO). The receiver implements the proposed SWR-BIST technique. The simulation results show that in the functional mode, the power consumption is 3.18mW in average. In the BIST mode, the power consumption of SWR-BIST is 6.35mW (at 16MHz clock), which is 40% lower than that of the traditional BIST (10.49mW). The receiver is implemented in UMC 0.18μm 1P6M technology. The measurement results confirm the effectiveness of the SWR-BIST.
|
|---|
