Highly-Efficient Low Noise Converter for DVS and Power Management System

• Main Authors: Hong-Wei Huang, 黃宏瑋
• Other Authors: Kuo, Sy-Yen
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/13863931095301995132

碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === A new high efficiency low noise dynamic voltage scaling (DVS) power management system (PMS) utilizing two regulation stages is described. The former stage of PMS consists of a pulse-width modulation (PWM) control mode and a pulse-frequency modulation (PFM) control mode. According to the output voltage and load current, the control scheme of former stage is switched automatically between both control modes by utilizing a load sensing circuit and looking efficient table up. The latter stage is used to regulate the voltage which is generated from former stage. It consists of two low drop-out (LDO) regulators, one is used with n-channel power device in output range from 0.65v~1.4v and the other is used with p-channel power device in output range from 1.45v~2.2v. By switching the control mode in overall structure of PMS, the maximum efficiency of 87.55% is attained. This chip is fabricated in TSMC 2P4M 0.35μm Mixed Signal process. The switching frequency of PWM and PFM are 500 kHz and 250 kHz, respectively, and the line regulation and load regulations are 4.2% and 0.0735%, respectively. The output voltage ripple is less then 0.15mv in the range of output voltage from 0.65v to 2.2v for load current from 3mA to 400mA and the supply voltage can be endured from 2.5v to 4.5v.