| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === In this thesis, the motivation, challenges, and solutions of burst-mode clock and data recovery (BMCDR) circuits for passive optical networks (PONs) are presented.
The need for clock and data recovery circuits is explained first. Then, the basic architecture of a PON is analyzed so that the BMCDR circuits can be realized. The motivation and the specifications related to BMCDR circuits are also introduced.
The existing BMCDR circuits are classified into three categories in this thesis. After introducing every category, a comparison in view of achievable data rate, locking time, power, area, and jitter performance is made. Summarizing the comparisons, the challenges manifest clearly. Thus, two 2.5Gbps BMCDR circuits are presented. Chapter 3 and chapter 4 give the details of these two circuits.
A digital-type BMCDR circuit using oversampling is presented. It is modified from [13]. However, with the modified algorithm, the critical path is shortened. A higher-speed (2.5Gbps) and low-power (33mW) BMCDR circuit is obtained. It is implemented in a standard 0.18um CMOS process and the area is 1.5mm x 1.01mm.
Besides the former circuit, a multi-band BMCDR circuit using frequency dividers is implemented. Instead of oversampling, this work is based on gated voltage-controlled-oscillator (GVCO) that is namely a stoppable VCO because it is composed of logic gates. Before the proposed GVCO, the analysis of VCO is made to understand the problem encountered when designing a 2.5Gbps GVCO-based BMCDR circuit. With the proposed GVCO and modified frequency dividers, multi-band operation (2488.32Mbps, 1244.16Mbps, 622.08Mbps, and 155.52Mbps) is achieved while consuming 70mW. In addition, the jitter tolerance of this burst-mode CDR circuit is also measured and analyzed. The chip is also implemented in a standard 0.18um CMOS process and the area is 1.48mm x 0.92mm.
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