| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === The flip-chip package gives the highest chip density of any packaging method
to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs.
In this thesis, we propose the first router for the flip-chip package. The router
can redistribute nets from wire-bonding pads to bump pads and then route each
of them. The router adopts a two-stage technique of global routing followed by
detailed routing. In global routing, we use the network flow algorithm to solve
the assignment problem from the wire-bonding pads to the bump pads, and then
create the global routing path for each net. The detailed routing consists of three
stages, cross point assignment, net ordering determination, and track assignment,
to complete the routing. Experimental results based on seven real designs from
the industry demonstrate that the router can reduce the total wirelength by 10.2%,
the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a
heuristic algorithm currently used in industry.
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