A 2.4GHz ISM Band Frequency Synthesizer with a Delta-Sigma Modulator

• Main Authors: Guo-Hau Lee, 李國豪
• Other Authors: Liang-Hung Lu
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/63429773876438628033

碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === In a wireless communication system, narrow channel spacing and fast switching time between channels are desirable to accommodate more users due to the limited frequency band. A fractional-N phase-locked-loop (PLL) architecture is a widely used technique to meet the demands. In order to alleviate the problems caused by fractional spurs and noises, the delta-sigma modulator (DSM) technique is adopted to reduce the phase noise within the synthesizer bandwidth. As a result, the fractional spurs and noises performance can be improved. A 2.4 GHz ISM-band fractional-N frequency synthesizer with a monolithic voltage-controlled oscillator is presented in this thesis. By utilizing the E-TSPC type prescaler, the divider circuit can achieve both high-speed frequency division and low power consumption. No power hunger preamplifier or buffer is needed to drive the divider. The chip is composed of a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO) and a multi-modulus divider (MMD). The required low-pass filter is provided by off-chip components in this design. The DSM output is provided by pattern generator. Fabricated in a TSMC 0.35-μm 2P4M CMOS technology, the power consumption of the synthesizer is 27mW. The measured phase noise performance in lock state is -97dBc/Hz @ 1MHz offset. The chip area is 894 × 855 μm2.