System-Level Performance/Power Evaluation Framework for SoC

• Main Authors: Chin-Chieh Huang, 黃靖傑
• Other Authors: Chia-Lin Yang
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/57445829109364777857

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 93 === With the improvement of semiconductor technology, it is now possible that we could construct the whole system on a single chip (SoC). SoC can reduce overall system cost, increase performance, lower power consumption, and reduce chip size. But it also increases the sys-tem design complexity. To facilitate early design space exploration for platform SoC, we are currently developing a system-level performance/power evaluation framework. A platform- based SoC contains a microprocessor, memory hierarchy, interconnected buses, peripherals,and a set of IP cores. For a platform SoC designer, it is challenging to determine platform components in view of performance and power at the early stage of the design °ow. The proposed system-level simulation framework provides cycle-accurate performance and power evaluation at the system-level through e±cient hardware-software co-simulation.